The present invention relates to a nonvolatile memory enabling electric erase and write and to a semiconductor integrated circuit such as a data processor called a microcomputer or a microprocessor equipped with the nonvolatile memory together with a central processing unit (also called a CPU), e.g., to a technique effective to be applied to a microcomputer equipped with a flash memory.
In the read operation of a flash memory, 1) a read bit line is precharged, 2) a word line is started up at a selective level such as a high level (“H”) to turn on a memory cell transistor, 3) upon flowing of a memory current via the memory cell transistor, the precharged bit line is drawn out to a low level (“L”), and 4) the potential of the bit line drawn out to the low level is sensed by a sense amp.
When a threshold voltage (Vth) of a memory cell transistor is lower than a word line potential (word line selected level), a bit line is discharged to read data “1”. When the Vth of the memory is higher than the word line potential, the bit line is not discharged to read data “0”. At fast read, the bit line capacity must be smaller to be discharged at high speed. Typically, a bit line hierarchical structure is employed. In the bit line load capacity, the drain capacity of the memory is dominant. In the bit line hierarchical structure, a bit line is divided into some blocks to provide a multiple sub-bit line structure. A memory is connected to the divided sub-bit lines. The sub-bit lines are connected via a hierarchical switch to a main bit line. When the bit line hierarchical structure is employed, the bit line load capacity is the total of a sub-bit line load obtained by summing the wiring capacity of sub-bit lines connected to a limited number of memories and the drain capacity of the memories connected and a main bit line load which is mainly a wiring capacity. This is a load capacity of a fraction of the case that all memories are connected to a main bit line without having a hierarchical structure. A memory current discharges these small loads fast to amplify the lowered bit line potential by a sense amp. When performing write, a hierarchical switch including a write word line is turned on to give a write pulse to a main bit line. As a result, the pulse passes through the hierarchical switch to be given to a sub-bit line. It is not applied to other sub-bit lines. As compared with the case that all memories are connected to a main bit line, time to add drain disturb can be significantly reduced.
As another fast read method, there is a structure having a plurality of divided memory arrays each having a read circuit and a write circuit (see Patent Document 1). For example, each of four divided memory arrays has a row decoder and a sense amp whose outputs are connected to a bus line. When there is an access, the highest order address is decided to operate any one of the arrays. Similarly, at write, the highest order address is decided to transfer write data from the bus line to any one of the write circuits.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2000-339983